1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, it relates to a structure of an MOS (Metal-Oxide-Semiconductor) dynamic RAM (Random Access Memory) including a trench structure and a method for manufacturing the same.
2. Description of the Prior Art
FIG. 1 is a diagram showing a structure of a memory cell portion of a conventional MOS dynamic RAM, FIG. 2 is a cross sectional view taken along a line II--II shown in FIG. 1, FIG. 3 is a cross sectional view taken along a line III--III shown in FIG. 1, FIG. 4 is a perspective view showing a structure of a memory cell portion of a dynamic RAM shown in FIG. 1, and FIG. 5 is an electric circuit diagram of a cell for constituting a dynamic RAM.
The MOS dynamic RAM shown in FIGS. 1 to 5, which is disclosed in, for example, Technical Digest, pp. 236-239, in International Electron Device Meeting 1984, comprises memory cells each having a single transistor and a single capacitor, as shown in FIG. 5. The basic operation is described in detail in a general textbook, for example, by W. N. Carr and J. P. Mize and translated by Ryo Terashima, entitled "MOS/LSI Design and Application", Electronics Digest (Inc.), 1977, P. 195 and hence, it is omitted. Only the operational principle is described in the following.
As shown in FIG. 4, a silicon substrate 1 and a capacitor electrode 9 are arranged such that a thin film 32 of silicon oxide by thermal oxidation, having, for example, a thickness of 10 to 20 nm, is interposed therebetween, where a memory capacitor 33 is formed. In order to reduce the area occupied by the memory capacitor 33, a trench 30 is formed in the silicon substrate 1 so that the opposing area of the memory capacitor 33 may be increased, as clear in comparison of FIG. 3 with FIG. 4. The memory capacitor 33 serves as a memory depending on whether charges are stored in the memory capacitor 33 or not. Word lines 5 and bit lines 7 are arranged orthogonal to each other in a matrix manner so that a particular one out of a large number of memory capacitors 33 arranged on an array may be selected when a write operation or a read operation are performed.
The word line 5 extends over the silicon substrate 1 and a silicon oxide film 2 formed thereon, where a channel 11 of an MOS transistor if formed. The MOS transistor is referred to as a transfer gate and serves as a switch for switching an electrical connection or disconnection between the memory capacitor 33 and the bit line 7. The transfer gate has one conduction terminal connected to the memory capacitor 33 through a diffusion layer 31 and other conduction terminal connected to the bit line 7 through a contact 10. Whether a signal transmitted through the bit line 7 bears charges or not (that is, a signal from the memory is at an "H" or an "L" level) is determined by a discriminator circuit referred to as a sense amplifier. In order to electrically isolate a cell from the other cell in the memory, an impurity diffusion layer 3 which is a region having high impurity concentration is formed in the bottom portion of the trench 30 in the memory capacitor 33, and an insulating material 4 such as silicon oxide is buried in the trenches other than the memory capacitor portions, so that buried insulator layers are formed. An interlayer insulating layer 6 is used to isolate the bit line 7 from the word line 5 and the capacitor electrode 9.
FIGS. 6A and 6B are perspective views for explaining a method for manufacturing a conventional dynamic RAM.
Referring now to FIGS. 6A and 6B, description is made on a method for manufacturing a conventional semiconductor device having a trench structure. In FIG. 6A, a trench structure 30 is formed on a major surface of a silicon substrate 1. In addition, in order to form an integrated circuit on the silicon substrate 1 by the subsequent processes, surfaces A and B which are separated side surfaces of the trench structure 30 and a surface C which is the major surface of the silicon substrate 1 must be electrically isolated from each other. Such electrical isolation on the surface of the semiconductor substrate is referred to as field isolation. In a conventional large scale integrated circuit (LSI) having no trench structure as shown in FIG. 6A, field isolation on the surface of the semiconductor substrate is performed by a so-called LOCOS (Local Oxidation of Silicon) process which is a selective oxidation process utilizing a silicon nitride film. Such a LOCOS process is disclosed in U.S. Pat. No. 3,544,858. However, an effective method for applying the LOCOS process to the side wall of the trench structure 30 of the semiconductor substrate has not been found. Thus, in the silicon substrate 1 having the trench structure 30 formed therein as shown in FIG. 6A, an insulating material 4 such as silicon oxide is filled in the trench 30 as shown in FIG. 6B, so that required field isolation is performed. In order to fill the insulating material 4, the entire inside of the trench structure 30 is temporarily filled with the insulating material 4 by chemical vapor deposition (CVD), a necessary portion is covered with resist by a photolithographic process, and the whole or a part of an unnecessary portion of the insulating material 4 are etched away. Therefore, electrical isolation on the surfaces A, B and C is achieved, so that the subsequent processes for manufacturing an integrated circuit are performed.
A conventional semiconductor substrate having a trench structure 30 is manufactured by the above described method. Therefore, in performing field isolation, the isolated region is covered with resist having margin (.alpha. and .beta. in FIG. 6B) required for compensating for misalignment of a mask in photolithography so that etching is performed. Therefore, the insulating material 4 extends in the lateral direction on the side surfaces A and B of the trench structure 30 as shown in FIG. 6B, so that the larger area is wasted for field isolation. In addition, it is difficult to hold the heights of the major surface of the silicon substrate 1 and the upper surface of the filled insulating material 4 at the same level. For example, a step occurs in the portion shown by .gamma. in FIG. 6B, so that a leak current increases in the subsequent processes for manufacturing an integrated circuit (for example, an MOS transistor).